Products  »  Jetson AGX / TX2 Camera Interface

The Jetson AGX / TX2 Camera Interface is the best way to connect MIPI CSI-2 cameras to your NVIDIA TX2 or AGX development system. It handles a wide variety of use cases, provides powerful FPGA-based frame triggering, and uses industry-standard flex cables for camera interconnect.

Key Features

• Designed to install onto NVIDIA AGX and TX2 Development Kit Carriers, as well as any third party carrier which uses the NVIDIA-specified camera interface pinout.
• Exposes 6x MIPI CSI-2 Camera Interfaces (2-lane) on 22-pin, 0.5mm pitch ribbon cable connectors.
• On-board Lattice ICE40UP5K FPGA provides independent or synchronized camera trigger and reset sigals. See section below for Trigger Details.
• Auxiliary Connector (6-pin JST GH) exposes additional 4 GPIO / sync / trigger signals from the FPGA.
• Camera logic power can be supplied via the Host (3.3v) or 1.8v thru 12v via a 2-pin Molex PICOLOCK connector. The FPGA controls downstream camera logic power via a single high-side switch IC.
• On-board PCA9548A I2C level-shifter and bus isolator allows duplicate I2C devices (imagers, EEPROM, IMU, etc) on each downstream ribbon cable.
• Solder jumpers allow Camera's 0 I2C bus to be changed from routing through the PCA9548A to a direct connection to the TX2/AGX "general purpose" I2C bus. This allows host-side software higher bandwidth to camera 0 (great for streaming IMU data) while cameras 1 through 5 share use of the host's "camera" I2C bus.
• PCA9548A bus 6 and 7 are exposed on Sparkfun Qwiic connectors for easy connection to external I2C devices. Solder jumpers allow for 3.3v or 1.8v power to be provided to each JST SH connector.

AGX / TX2 Camera Interface

$160

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FPGA-Based Camera Triggering

The FPGA provides a number of different triggering modes and all triggers are effected by a configurable trigger mask register. CAM0 is bit 0, CAM1 is bit 1, etc. A bit must be set for that output to follow the active trigger.

• Stop: Any active trigger (interval, oneshot, constant, round-robin, or follower) is immediately ended.
• Interval: Repetitious trigger with a specified interval and duration. Trigger duration (length of the trigger pulse) is configuratble from between 1 ms to 255 ms and trigger interval (time between the start of one trigger pulse and the next one) is configurable from between 1 ms and 255 ms.
• Oneshot: A single trigger pulse of between 1 ms and 255 ms is emitted.
• Constant: Triggers go high and stay high.
• Round-Robin: Repetitious triggering like interval, but each trigger pulse is only emitted on a single camera. The next trigger emits on the next sucessive camera (following the active mask), and so on.
• Follower: Auxiliary input 0 or 1 can be selected as the trigger source. Active trigger outputs follow the state of the selected input. This allows one TX2 or AGX host to control the triggering of cameras connected to a seconds TX2 or AGX host.

Open FPGA Gateware

Not only is the FPGA-based triggering gateware powerful and flexible, it is open source and is built using an open-source iCE40 FPGA toolchain.

The gateware is written in nMigen, an open-source toolchain for developing hardware based on synchronous digital logic using the Python programming language. nMigen aims to be easy to learn and use, reduce or eliminate common coding mistakes, and simplify the design of complex hardware with reusable components.

I2C Multiplexing and Level Shifting

The I2C level-shifter / multiplexer and configurable jumpers allow for connection of external I2C sensors and devices, for different I2C voltages to be used for cameras and those external I2C devices, and direct or multiplexed connection to Camera 0.

Resources

•   FPGA Gateware GitHub Repository
•   Data & Power Block Diagram (PDF)